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sic788, SIC788A www.vishay.com vishay siliconix s15-0163-rev. c, 02-feb-15 1 document number: 62985 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 50 a vrpower ? integrated power stage description the sic788 and SIC788A are integrated power stage solutions optimized for synchro nous buck applications to offer high current, high efficiency, and high power density performance. packag ed in vishays proprietary 6 mm x 6 mm mlp package, sic788 and SIC788A enable voltage regulator designs to de liver up to 50 a continuous current per phase. the internal power mosfets utilize vishays state-of-the-art gen iv trench fet technology that delivers industry benchmark performan ce to significantly reduce switching and conduction losses. the sic788 and SIC788A incorporate an advanced mosfet gate driver ic that features high current driving capability, adaptive dead-time control, an integrated bootstrap schottky diode, a thermal warning (thwn) that alerts the system of excessive junction temperature, and skip mode (smod#) to improve light load efficiency. the drivers are also compatible with a wide range of pwm controllers and supports tri-state pwm, 3.3 v (SIC788A) / 5 v (sic788) pwm logic. features ? thermally enhanced powerpak ? mlp66-40l package ? vishays gen iv mosfet technology and a low-side mosfet with integrated schottky diode ? delivers up to 50 a continuous current ? 95 % peak efficiency ? high frequency operation up to 1.5 mhz ? power mosfets optimize d for 12 v input stage ? 3.3 v (SIC788A) / 5 v (sic788) pwm logic with tri-state and hold-off ? smod# logic for light lo ad efficiency improvement ? low pwm propagation delay (< 20 ns) ? thermal monitor flag ? faster enable / disable ? under voltage lockout for v cin ? material categorization: fo r definitions of compliance please see www.vishay.com/doc?99912 applications ? multi-phase vrds for cpu, gpu, and memory typical application diagram fig. 1 - sic788 and SIC788A typical application diagram pwm controller g ate driver 5v v in v out v cin s mod# d s bl# pwm thwn v drv g h v in boot v s wh p g nd g l c g nd pha s e
sic788, SIC788A www.vishay.com vishay siliconix s15-0163-rev. c, 02-feb-15 2 document number: 62985 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pinout configuration fig. 2 - sic788 and SIC788A pin configuration pin description pin number name function 1 smod# low-side gate turn -off logic. active low 2v cin supply voltage for internal logic circuitry 3v drv supply voltage for internal gate driver 4 boot high-side driver bootstrap voltage 5, 37, 41 c gnd analog ground for the driver ic 6 gh high-side gate signal 7 phase return path of high-side gate driver 8 to 14, 42 v in power stage input voltage. drain of high-side mosfet 15, 29 to 35, 43 v swh switch node of the power stage 16 to 28 p gnd power ground 36 gl low-side gate signal 38 thwn thermal warning open drain output 39 dsbl# disable pin. active low 40 pwm pwm control input ordering information part number package marking code option SIC788Acd-t1-ge3 powerpak ? mlp66-40l SIC788A 3.3 v pwm optimized sic788cd-t1-ge3 sic788 5 v pwm optimized SIC788Adb and sic788d b reference board s mod# 1 vcin 2 vdrv 3 boot 4 c g nd 5 g h 6 pha s e 7 vin 8 vin 9 vin 10 vin 11 vin 12 vin 13 vin 14 v s wh 15 p g nd 16 p g nd 17 p g nd 18 p g nd 19 p g nd 20 28 p g nd 27 p g nd 26 p g nd 25 p g nd 24 p g nd 23 p g nd 22 p g nd 21 p g nd 30 v s wh 29 v s wh 31 v s wh 32 v s wh 33 v s wh 34 v s wh 35 v s wh 36 g l 37 c g nd 38 thwn 39 d s bl# 40 pwm 41 c g nd 42 vin 43 v s wh top view 1 s mod# 2 vcin 3 vdrv 4 boot 5 c g nd 6 g h 7 pha s e 8 vin 9 vin 10 vin vin 11 vin 12 vin 13 vin 14 v s wh 15 p g nd 16 p g nd 17 p g nd 18 p g nd 19 p g nd 20 p g nd 28 p g nd 27 p g nd 26 p g nd 25 p g nd 24 p g nd 23 p g nd 22 p g nd 21 v s wh 30 v s wh 29 31 v s wh 32 v s wh 33 v s wh 34 v s wh 35 v s wh 36 g l 37 c g nd 38 thwn 39 d s bl# 40 pwm bottom view 41 c g nd 42 vin 43 v s wh
sic788, SIC788A www.vishay.com vishay siliconix s15-0163-rev. c, 02-feb-15 3 document number: 62985 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes (1) the specification values indicated ac is v swh to p gnd , -8 v (< 20 ns, 10 j), min. and 30 v (< 50 ns), max. (2) the specification value indicates ac voltage is v boot to p gnd , 36 v (< 50 ns) max. (3) the specification value indicates ac voltage is v boot to v phase , 8 v (< 20 ns) max. (4) output current rated with te sting evaluation board at t a = 25 c with natural convecti on cooling. the rating is li mited by the peak evaluation board temperature, t j = 150 c, and varies depending on the op erating conditions and pcb layout. this rating may be changed with different application settings. stresses beyond those listed under absolute maximum ratings ma y cause permanent damage to th e device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those in dicated in the operational sectio ns of the specifications is not implied. exposure to absolute maximum rating conditions for extended pe riods may affect device reliability. absolute maximum ratings electrical parameter conditions limit unit input voltage v in -0.3 to +25 v control logic supply voltage v cin -0.3 to +7 drive supply voltage v drv -0.3 to +7 switch node (dc voltage) v swh -0.3 to +25 switch node (ac voltage) (1) -8 to +30 boot voltage (dc voltage) v boot 32 boot voltage (ac voltage) (2) 38 boot to phase (dc voltage) v boot- phase -0.3 to +7 boot to phase (ac voltage) (3) -0.3 to +8 all logic inputs and outputs (pwm, dsbl#, and thwn) -0.3 to v cin + 0.3 output current, i out(av) (4) f s = 300 khz, v in = 12 v, v out = 1.8 v 50 a f s = 1 mhz, v in = 12 v, v out = 1.8 v 40 max. operating junction temperature t j 150 c ambient temperature t a -40 to +125 storage temperature t stg -65 to +150 electrostatic disc harge protection human body model, jesd22-a114 5000 v charged device mo del, jesd22-c101 1000 recommended operating range electrical parameter mi nimum typical maximum unit input voltage (v in )4.5-18 v drive supply voltage (v drv ) 4.555.5 control logic supply voltage (v cin ) 4.555.5 boot to phase (v boot-phase , dc voltage) 4 4.5 5.5 thermal resistance from junction to pad - 1 - c/w thermal resistance from junction to case - 2.5 -
sic788, SIC788A www.vishay.com vishay siliconix s15-0163-rev. c, 02-feb-15 4 document number: 62985 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 electrical specifications (dsbl# = smod# = 5 v, v in = 12 v, v drv and v cin = 5 v, t a = 25 c) parameter symbol test condition limits unit min. typ. max. power supply control logic supply current i vcin v dsbl# = 0 v, no switching, v pwm = float - 85 - a v dsbl# = 5 v, no switching, v pwm = float - 290 - v dsbl# = 5 v, f s = 300 khz, d = 0.1 - 295 - drive supply current i vdrv f s = 300 khz, d = 0.1 - 9 15 ma f s = 1 mhz, d = 0.1 - 30 - v dsbl# = 0 v, no switching - 30 - a v dsbl# = 5 v, no switching - 55 - bootstrap supply bootstrap diode forward voltage v f i f = 2 ma 0.4 v pwm control input (sic788) rising threshold v th_pwm_r 3.4 3.7 4.0 v falling threshold v th_pwm_f 0.72 0.9 1.1 tri-state voltage v tri v pwm = float - 2.3 - tri-state rising threshold v tri_th_r 0.9 1.15 1.38 tri-state falling threshold v tri_th_f 3.1 3.35 3.6 tri-state rising threshold hysteresis v hys_tri_r - 225 - mv tri-state falling threshold hysteresis v hys_tri_f - 325 - pwm input current i pwm v pwm = 5 v - - 350 a v pwm = 0 v - - -350 pwm control input (SIC788A) rising threshold v th_pwm_r 2.2 2.45 2.7 v falling threshold v th_pwm_f 0.72 0.9 1.1 tri-state voltage v tri v pwm = float - 1.8 - tri-state rising threshold v tri_th_r 0.9 1.15 1.38 tri-state falling threshold v tri_th_f 1.95 2.2 2.45 tri-state rising threshold hysteresis v hys_tri_r - 225 - mv tri-state falling threshold hysteresis v hys_tri_f - 275 - pwm input current i pwm v pwm = 3.3 v - - 225 a v pwm = 0 v - - -225 timing specifications tri-state to gh/gl rising propagation delay t pd_tri_r no load, see fig. 4 -30- ns tri-state hold-off time t tsho - 130 - gh - turn off propagation delay t pd_off_gh -18- gh - turn on propagation delay (dead time rising) t pd_on_gh -15- gl - turn off propagation delay t pd_off_gl -12- gl - turn on propagation delay (dead time falling) t pd_on_gl -8- dsbl# low to gh/gl falling propagation delay t pd_dsbl#_f fig. 5 - 15 - dsbl# high to gh/gl rising propagation delay t pd_dsbl#_r fig. 5 - 20 - pwm minimum on-time t pwm_on_min 30 - - dsbl# smod# input dsbl# logic input voltage v ih_dsbl# input logic high 2 - - v v il_dsbl# input logic low - - 0.8 smod# logic input voltage v ih_smod# input logic high 2 - - v il_smod# input logic low - - 0.8
sic788, SIC788A www.vishay.com vishay siliconix s15-0163-rev. c, 02-feb-15 5 document number: 62985 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes (1) typical limits are established by characterization and are not production tested. (2) guaranteed by design. detailed operational description pwm input with tri-state function the pwm input receives the pwm control signal from the vr controller ic. the pwm input is designed to be compatible with standard controllers using two state logic (h and l) and advanced controllers that incorporate tri-state logic (h, l and tri-state) on the pwm output. for two state logic, the pwm input operates as follows. when pwm is driven above v pwm_th_r the low-side is turned off and the high-side is turned on. when pwm in put is driven below v pwm_th_f the high-side is turned off and the low-side is turned on. for tri-state logic, the pwm input operates as previously stated for driving the mosfets when pwm is logic high and logic low. however, there is a third state that is entered as the pwm output of tri-state compatible controller enters its high impedance state during shut -down. the high impedance state of the controllers pwm output allows the sic788 and SIC788A to pull the pwm input into the tri-state region (see definition of pwm logic and tri-st ate, fig. 4). if the pwm input stays in this region for the tri-state hold-off period, t tsho , both high-side and low-side mosfets are turned off. the function allows the vr phas e to be disabled without negative output volt age swing caused by inductor ringing and saves a schottky diode clamp. the pwm and tri-state regions are separated by h ysteresis to prevent false triggering. the SIC788A incorporates pwm voltage thresholds that are compatible with 3.3 v logic and the sic788 thresholds are compatible with 5 v logic. disable (dsbl#) in the low state, the dsbl# pi n shuts down the driver ic and disables both high-side and low-side mosfets. in this state, standby current is mi nimized. if dsbl# is left unconnected, an internal pull-d own resistor will pull the pin to c gnd and shut down the ic. pre-charger function when dsbl# is driven from below v il_dsbl# to above v ih_dsbl# the low-side is turned on for a short duration (60 ns typical) to refresh the boot capacitor in case it has been discharged due to the driver being in standby for a long period of time. diode emulation mode (smod#) when smod# is logic low diode emulation mode is enabled and the low-side is turned o ff. this is a non-synchronous conversion mode that improves light load efficiency by reducing switching losses. co nducted losses that occur in synchronous buck regulators when inductor current is negative can also be reduced. circuitry in the external controller ic detects when inductor current crosses zero and drives smod# below v il_smod# turning the low-side mosfet off. the function can be also be used for a pre-biased output voltage. if smod# is left unconnected, an internal pull up resistor will pull the pin to v cin (logic high) to disable the smod# function. thermal shutdown warning (thwn) the thwn pin is an open drain signal that flags the presence of excessive junction te mperature. connect, with a maximum of 20 k , to v cin . an internal temperature sensor detects the junction temperature. the temperature threshold is 160 c. when this junction temperature is exceeded the thwn flag is set. when the junction temperature drops below 135 c the device will clear the thwn signal. the sic788 and SIC788A do not stop operation when the flag is set. the decision to shutdown must be made by an external thermal control function. voltage input (v in ) this is the power input to th e drain of the high-side power mosfet. this pin is connected to the high power intermediate bus rail. protection under voltage lockout v uvlo v cin rising, on threshold - 3.7 4.1 v v cin falling, off threshold 2.7 3.1 - under voltage lockout hysteresis v uvlo_hyst - 575 - mv thwn flag set (2) t thwn_set - 160 - c thwn flag clear (2) t thwn_clear - 135 - thwn flag hysteresis (2) t thwn_hyst -25- thwn output low v ol_thwn i thwn = 2 ma - 0.02 - v electrical specifications (dsbl# = smod# = 5 v, v in = 12 v, v drv and v cin = 5 v, t a = 25 c) parameter symbol test condition limits unit min. typ. max.
sic788, SIC788A www.vishay.com vishay siliconix s15-0163-rev. c, 02-feb-15 6 document number: 62985 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 switch node (v swh and phase) the switch node, v swh , is the circuit power stage output. this is the output applied to the power inductor and output filter to deliver the output for the buck converter. the phase pin is internally connected to the switch node, v swh . this pin is to be used exclusively as the return pin for the boot capacitor. a 20 k resistor is connected between gh and phase to provide a discharge path for the hs mosfet in the event that v cin goes to zero while v in is still applied. ground connections (c gnd and p gnd ) p gnd (power ground) should be externally connected to c gnd (control signal ground). the layout of the printed circuit board should be such that the inductance separating c gnd and p gnd is minimized. transient differences due to inductance effects between these two pins should not exceed 0.5 v control and drive supp ly voltage input (v drv , v cin ) v cin is the bias supply for the gate drive control ic. v drv is the bias supply for the gate drivers. it is recommended to separate these pins through a resistor. this creates a low pass filtering effect to avoid coupling of high frequency gate drive noise into the ic. bootstrap circuit (boot) the internal bootstrap diode and an external bootstrap capacitor form a charge pump that supplies voltage to the boot pin. an integrated boot strap diode is incorporated so that only an external capacitor is necessary to complete the bootstrap circuit. connect a b oot strap capacitor with one leg tied to boot pin and the other tied to phase pin. shoot-through protection and adaptive dead time the sic788 and SIC788A have an internal adaptive logic to avoid shoot through and optimize dead time. the shoot through protection ensures that both high-side and low-side mosfets are not turned on at the same time. the adaptive dead time control operates as follows. the high-side and low-side gate voltages are monitored to prevent the mosfet turning on from tuning on until the other mosfets gate voltage is suffi ciently low (< 1 v). built in delays also ensure that one power mosfet is completely off, before the other can be turned on. this feature helps to adjust dead time as gate transitions change with respect to output current and temperature. under voltage lockout (uvlo) during the start up cycle, the uvlo disables the gate drive, holding high-side and low-side mosfet gates low, until the supply voltage rail has reached a point at which the logic circuitry can be safely activated. the sic788 and SIC788A also incorporate logic to clamp the gate drive signals to zero when the uvlo falling edge triggers the shutdown of the device. as an added precaution, a 20 k resistor is connected betwee n gh and phase to provide a discharge path for the hs mosfet. functional block diagram fig. 3 - sic788 and SIC788A functional block diagram pwm v cin c g nd d s bl# 20k boot v s wh v drv g l p g nd + - v ref = 1 v v ref = 1 v g l + - anti-cro ss conduction control logic v drv v cin pwm logic control & s tate machine uvlo thermal monitor & warning thwn s mod# v in pha s e g h
sic788, SIC788A www.vishay.com vishay siliconix s15-0163-rev. c, 02-feb-15 7 document number: 62985 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pwm timing diagram fig. 4 - definition of pwm logic and tri-state device truth table dsbl# smod# pwm gh gl open x x l l lxxll hllll hlhhl hltri-statell hhl lh hhhhl hhtri-statel l v th_pwm_r v th_pwm_f v th_tri_r v th_tri_f pwm g h g l t pd_off_ g l t t s ho t pd_on_ g h t pd_off_ g h t pd_on_ g l t t s ho t pd_tri_r t pd_tri_r
sic788, SIC788A www.vishay.com vishay siliconix s15-0163-rev. c, 02-feb-15 8 document number: 62985 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 operation timing diagram: dsbl# fig. 5 - dsbl# propagation delay pwm d s bl # g h g l t pwm d s bl # g h g l t d s bl # high to g h ri s ing propagation delay d s bl# high to g l r i s ing propagation delay enable pwm d s bl # g h g l d s bl# low to g h falling propagation delay t d s bl# low to g l falling propagation delay pwm d s bl # g h g l t di s able
sic788, SIC788A www.vishay.com vishay siliconix s15-0163-rev. c, 02-feb-15 9 document number: 62985 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 electrical characteristics test condition: v in = 12 v, v drv = v cin = 5 v, dsbl# = smod# = 5 v, v out = 1.8 v, l out = 250 nh (dcr = 0.32 m ), t a = 25 c, natural convection cooling (all po wer loss and normalized power loss curves show sic788 and SIC788A lo sses only unless otherwise stated ) fig. 6 - efficiency vs. output current fig. 7 - efficiency vs. output current fig. 8 - power loss vs. switching frequency fig. 9 - power loss vs. output current fig. 10 - power loss vs. output current fig. 11 - safe operating area 55 60 65 70 75 80 85 90 95 0 4 8 12 16 20 24 28 32 36 40 efficiency (%) output current, i out (a) complete converter efficiency p in = [(v in x i in ) + 5 v x (i vdrv + i vcin )] p out = v out x i out , mea s ured at output capacitor 1 mhz 800 khz 500 khz 300 khz 55 60 65 70 75 80 85 90 95 0 4 8 12 16 20 24 28 32 36 40 efficiency (%) output current, i out (a) f s = 500 khz v out = 0.7 v v out = 0.8 v v out = 0.9 v v out = 1 v 0.60 0.75 0.90 1.05 1.20 1.35 1.50 1.65 1.80 200 300 400 500 600 700 800 900 1000 1100 1200 normalized power lo ss s witching fre q uency, f s (khz) 0.0 1.5 3.0 4.5 6.0 7.5 9.0 10.5 12.0 0 4 8 12 16 20 24 28 32 36 40 power lo ss , p l (w) output current, i out (a) 1 mhz 800 khz 500 khz 300 khz 0.0 1.5 3.0 4.5 6.0 7.5 9.0 10.5 12.0 0 4 8 12 16 20 24 28 32 36 40 power lo ss , p l (w) output current, i out (a) f s = 500 khz v out = 0.7 v v out = 0.8 v v out = 0.9 v v out = 1.0 v 0 5 10 15 20 25 30 35 40 45 0 153045607590105120135150 output current, i out (a) pcb temperature, t pcb ( c) 1 mhz 300 khz
sic788, SIC788A www.vishay.com vishay siliconix s15-0163-rev. c, 02-feb-15 10 document number: 62985 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 12 - driver supply current vs. output current fig. 13 - uvlo threshold vs. temperature fig. 14 - pwm threshold vs. temperature (SIC788A) fig. 15 - boot diode forward voltage vs. temperature fig. 16 - pwm threshol d vs. temperature (sic788) 0.88 0.92 0.96 1.00 1.04 1.08 1.12 1.16 1.20 0 4 8 12 16 20 24 28 32 36 40 normalized driver s upply current output current, i out (a) 1 mhz 300 khz 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 -60 -40 -20 0 20 40 60 80 100 120 140 control logic s upply voltage, v cin (v) temperature ( c) v uvlo_fallin g v uvlo_ri s in g s hold voltage, v pwm (v) temperature ( c) v tri_th_r v tri_th_f v tri v th_pwm_r v th_pwm_f 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 -60 -40 -20 0 20 40 60 80 100 120 140 boot diode forward voltage, v f (v) temperature ( c) i f = 2 ma 0.0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 -60 -40 -20 0 20 40 60 80 100 120 140 pwm thre s hold voltage, v pwm (v) temperature ( c) v tri_th_r v tri_th_f v tri v th_pwm_r v th_pwm_f
sic788, SIC788A www.vishay.com vishay siliconix s15-0163-rev. c, 02-feb-15 11 document number: 62985 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 17 - pwm threshold vs. dr iver supply voltage (SIC788A) fig. 18 - dsbl# threshold vs. temperature fig. 19 - smod# threshold vs. temperature fig. 20 - pwm threshold vs. driver supply voltage (sic788) fig. 21 - dsbl# threshold vs. driver supply voltage fig. 22 - smod# threshold vs. driver supply voltage 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 pwm thre s hold voltage, v pwm (v) driver s upply voltage, v cin (v) v th_pwm_f v tri v th_pwm_r v tri_th_f v tri_th_r 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 -60 -40 -20 0 20 40 60 80 100 120 140 d s bl# thre s hold voltage, v d s bl# (v) temperature ( c) v il_d s bl# v ih_d s bl# 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 -60 -40 -20 0 20 40 60 80 100 120 140 s mod# thre s hold voltage, v s mod# (v) temperature ( c) v il_ s mod# v ih_ s mod# 0.0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 pwm thre s hold voltage, v pwm (v) driver s upply voltage, v cin (v) v th_pwm_f v th_pwm_r v tri_th_f v tri_th_r v tri 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 d s bl# thre s hold voltage, v d s bl# (v) driver s upply voltage, v cin (v) v ih_d s bl# v il_d s bl# 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 s mod# thre s hold voltage, v s mod# (v) driver s upply voltage, v cin (v) v ih_ s mod# v il_ s mod#
sic788, SIC788A www.vishay.com vishay siliconix s15-0163-rev. c, 02-feb-15 12 document number: 62985 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 23 - dsbl# pull-dow n current vs. temperature fig. 24 - driver quiescent current vs. temperature fig. 25 - smod# pull-up current vs. temperature fig. 26 - driver quiescent current vs. temperature 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 -60 -40 -20 0 20 40 60 80 100 120 140 d s bl# pull-down current, i d s bl# (ua) temperature ( c) 40 60 80 100 120 140 160 180 200 -60 -40 -20 0 20 40 60 80 100 120 140 driver s upply current, i vdvr & i vcin (v) temperature ( c) v d s bl# = 0 v -12.0 -11.5 -11.0 -10.5 -10.0 -9.5 -9.0 -8.5 -8.0 -60 -40 -20 0 20 40 60 80 100 120 140 s mod# pull-up current, i s mod# (ua) temperature ( c) v s mod# = 0 v 270 290 310 330 350 370 390 410 430 -60 -40 -20 0 20 40 60 80 100 120 140 driver s upply current, i vdvr & i vcin (v) temperature ( c) v pwm = float
sic788, SIC788A www.vishay.com vishay siliconix s15-0163-rev. c, 02-feb-15 13 document number: 62985 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pcb layout recommendations step 1: v in / p gnd planes and decoupling 1. layout v in and p gnd planes as shown above 2. ceramic capacitors should be placed directly between v in and p gnd , and as close as possible to ic for best decoupling effect 3. different ceramic capacitor values and packages should be used to cover entire decoupling spectrum, e.g. 1210, 0805, 0603, and 0402 4. smaller capacitance values, placed closer to the ics v in pin(s), result in better hi gh frequency noise absorbing step 2: v swh plane 1. connect output inductor to ic with large plane to lower resistance 2. v swh plane also serves as a heat-sink for low-side mosfet. please make the plane wide and short to achieve best thermal path 3. if a snubber network is required, place components as shown above step 3: v cin / v drv input filter 1. v cin / v drv input filter ceramic capacitors should be placed as close as possible to ic. it is recommended to connect two capacitors separately 2. v cin capacitor should be pl aced between pin 2 and pin 37 (c gnd of driver ic) to achieve best noise filtering 3. v drv capacitor should be pl aced between pin 3 and p gnd to provide maximum inst antaneous driver current for low-side mosfet during switching cycle. p gnd can be connected to inner ground plane through vias, as shown above 4. pin 5 and pin 37 should be connected with c gnd pad, as shown above 5. for connecting v cin to c gnd , it is recommended to use a large plane to reduce parasitic inductance step 4: boot resistor and capacitor placement 1. the components need to be placed as close as possible to ic, directly between phase (pin 7) and boot (pin 4) 2. to reduce parasitic inductance, 0402 package size can be used v in v s wh c g nd v in plane p g nd plane p g nd plane v s wh s nubber c g nd p g nd c vcin c vdrv via s for ground connection c g nd
sic788, SIC788A www.vishay.com vishay siliconix s15-0163-rev. c, 02-feb-15 14 document number: 62985 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 step 5: signal routing 1. route the pwm, smod#, dsbl#, and thwn signal traces out of the top right corner, next to pin 1 2. the pwm signal is a very important signal, both signal and return traces should not cross any power nodes on any layer 3. it is best to shield these traces from power switching nodes, e.g. v swh , with a gnd island to improve signal integrity step 6: adding thermal relief vias 1. thermal relief vias can be added to the v in and c gnd pads to utilize inner layers for high-current and thermal dissipation 2. to achieve better thermal perf ormance, additional vias can be added to v in and p gnd planes 3. the v swh pad is a noise source and it is not recommended to place vias on this pad 4. 8 mil vias for pads and 10 mils vias for planes are the optimal sizes. vias on pad may drain solder during assembly and cause assembly issues. please consult with the assembly house for guidelines step 7: ground connection 1. it is recommended to make the entire first inner layer (below top layer) the ground plane 2. the ground plane provides analog ground and power ground connections 3. the ground plane provide s shielding between noise source on top layer and sign al traces on bottom layer p g nd c g nd c g nd v in plane p g nd plane v s wh c g nd v in g nd plane c g nd
sic788, SIC788A www.vishay.com vishay siliconix s15-0163-rev. c, 02-feb-15 15 document number: 62985 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 recommended land pattern powerpak ? mlp66-40l in millimeters 1 1 0.025 0.100 0.100 0.100 0.100 0.025 40 0.100 0.100 0.100 0.100 0.100 0.100 0.600 2.600 1.700 0.320 0.310 40 2.200 2.200 0.276 0.276 0.200 4.600
sic788, SIC788A www.vishay.com vishay siliconix s15-0163-rev. c, 02-feb-15 16 document number: 62985 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 package outline drawing mlp66-40l vishay siliconix maintains worldw ide manufacturing ca pability. products may be manufactured at one of several qualified locatio ns. reliability da ta for silicon technology and package reliability represent a composite of all qu alified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?62985 . 40 1 2 x 2 x pin 1 dot by marking mlp66-40l (6 mm x 6 mm) 10 11 20 21 30 31 56 4 top view bottom view side view a b c d 0.10 c b e 0.10 c a a 0.08 c a1 a2 0.41 k2 k1 d2-1 pin #1 dent e2-1 e d2-3 d2-2 e2-3 e2-2 (nd-1)x e ref. (nd-1)x e ref. 0.10 m c a b dim. millimeters inches min. nom. max. min. nom. max. a 0.70 0.75 0.80 0.027 0.029 0.031 a1 0.00 - 0.05 0.000 - 0.002 a2 0.20 ref. 0.008 ref. b 0.20 0.25 0.30 0.078 0.098 0.011 d 6.00 bsc 0.236 bsc e 0.50 bsc 0.019 bsc e 6.00 bsc 0.236 bsc l 0.35 0.40 0.45 0.013 0.015 0.017 n40 40 nd 10 10 ne 10 10 d2-1 1.45 1.50 1.55 0.057 0.059 0.061 d2-2 1.45 1.50 1.55 0.057 0.059 0.061 d2-3 2.35 2.40 2.45 0.095 0.094 0.096 e2-1 4.35 4.40 4.45 0.171 0.173 0.175 e2-2 1.95 2.00 2.05 0.076 0.078 0.080 e2-3 1.95 2.00 2.05 0.076 0.078 0.080 k1 0.73 bsc 0.028 bsc k2 0.21 bsc 0.008 bsc
package information www.vishay.com vishay siliconix revision: 12-jan-15 1 document number: 64846 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 powerpak ? mlp66-40 case outline notes 1. use millimeters as the primary measurement 2. dimensioning and tolerances conform to asme y14.5m. - 1994 3. n is the number of terminals. nd is the number of terminals in x-direction and ne is the number of terminals in y-direction 4. dimension b applies to plated terminal and is m easured between 0.20 mm and 0.25 mm from terminal tip 5. the pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of packag e body 6. exact shape and size of this feature is optional 7. package warpage max. 0.08 mm 8. applied only for terminals dim. millimeters inches min. nom. max. min. nom. max. a (8) 0.70 0.75 0.80 0.027 0.029 0.031 a1 0.00 - 0.05 0.000 - 0.002 a2 0.20 ref. 0.008 ref. b (4) 0.20 0.25 0.30 0.078 0.098 0.011 d 6.00 bsc 0.236 bsc e 0.50 bsc 0.019 bsc e 6.00 bsc 0.236 bsc l 0.35 0.40 0.45 0.013 0.015 0.017 n (3) 40 40 nd (3) 10 10 ne (3) 10 10 d2-1 1.45 1.50 1.55 0.057 0.059 0.061 d2-2 1.45 1.50 1.55 0.057 0.059 0.061 d2-3 2.35 2.40 2.45 0.095 0.094 0.096 e2-1 4.35 4.40 4.45 0.171 0.173 0.175 e2-2 1.95 2.00 2.05 0.076 0.078 0.080 e2-3 1.95 2.00 2.05 0.076 0.078 0.080 k1 0.73 bsc 0.028 bsc k2 0.21 bsc 0.008 bsc ecn: t14-0826-rev. b, 12-jan-15 dwg: 5986 40 1 2 x 2 x pin 1 dot by marking mlp66-40 (6 mm x 6 mm) 10 11 20 21 30 31 56 4 top view bottom view side view a b c d 0.10 c b e 0.10 c a a 0.0 8 c a1 a2 0.41 k2 k1 d2-1 e2-1 e d2-3 d2-2 e2-3 e2-2 ( n d-1)x e ref. ( n d-1)x e ref. 0.10 m c a b
pad pattern www.vishay.com vishay siliconix revision: 28-feb-14 1 document number: 67964 for technical questions, contact: analogswitchtechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 recommended land pattern powerpak ? mlp66-40l 1 1 0.025 0.100 0.100 0.100 0.100 0.025 40 0.100 0.100 0.100 0.100 0.100 0.100 0.600 2.600 1.700 0.320 0.310 40 2.200 2.200 0.276 0.276 0.200 4.600 all dimen s ion s are in milimeter s
legal disclaimer notice www.vishay.com vishay revision: 08-feb-17 1 document number: 91000 disclaimer ? all product, product specifications and data ar e subject to change with out notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of th e products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product , (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all implied warranties, includ ing warranties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain types of applicatio ns are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular applic ation. it is the customers responsibility to validate tha t a particular product with the prope rties described in the product sp ecification is suitable for use in a particular application. parameters provided in datasheets and / or specifications may vary in different ap plications and perfor mance may vary over time. all operating parameters, including ty pical parameters, must be va lidated for each customer application by the customer s technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product could result in personal injury or death. customers using or selling vishay product s not expressly indicated for use in such applications do so at their own risk. please contact authorized vishay personnel to obtain writ ten terms and conditions rega rding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners. ? 2017 vishay intertechnology, inc. all rights reserved

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